Many kinds of Integrated circuits (IC's) are prone to damage and failure from an electro-static-discharge (ESD) pulse. ESD failures that occur in the factory contribute to lower yields. ESD failures may also occur in the field when an end-user touches a device.
Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Other ESD structures use an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage, thus consuming less power and producing less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted, by relatively small capacitively-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
FIG. 1 shows a chip with several ESD-protection clamps. Core circuitry 20 contains core transistors 22, 24, which have a small channel length and can be damaged by currents at relatively low voltages. Core circuitry 20 receives a power supply voltage VDD, such as 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in core circuitry 20.
Protection from ESD pulses may be provided on each I/O pad, and by power clamp 26. Power clamp 26 is coupled between VDD and ground (VSS), and shunts current from an ESD pulse between the power rails.
Some cross-coupling may occur between different pads and core circuitry 20, such as through substrates and capacitances. An ESD pulse applied to one I/O pad 10 may be coupled into core circuitry 20 by this cross-coupling, causing damage to transistors 22, 24 in core circuitry 20. Power clamp 26 may shunt enough current from the ESD pulse to reduce such cross-coupling to prevent damage. ESD pulses applied to I/O pins may still couple into core circuitry 20, such as through power lines, but power clamp 26 may then be activated to reduce potential damage.
Power clamp 26 may also turn on for other ESD pulses such as those applied to I/O pins, when the ESD pulse is shunted through a diode in the I/O pin's ESD-protection structure to the internal VDD rail, causing an indirect VDD-to-VSS ESD pulse. For example, an ESD pulse applied to I/O pad 10 may cause ESD protection device 12 to turn on to conduct to VDD.
Each I/O pad 10 may be outfitted with one or more ESD protection devices 12, 16 to protect against various possibilities. ESD protection device 16 turns on for a positive ESD pulse applied from ground to I/O pad 10, while ESD protection device 18 turns on for a positive ESD pulse applied from ground to I/O pad 10. Likewise, ESD protection device 12 turns on for a positive ESD pulse applied from I/O pad 10 to VDD while ESD protection device 14 turns on for a positive ESD pulse applied from I/O pad 11 to VDD. Power clamp 26 may also turn on in some situations.
Some prior-art ESD protection structures have large-area capacitors, resistors, or transistors. Large size devices are expensive and undesirable. Some prior-art ESD-protection devices are not suited for standard CMOS processes, such as ESD-protection devices that use insulator layers in Silicon-On-Insulator (SOI) processes.
Diodes have been uses as ESD-protection structures, but the diode's I-V characteristics allow for high voltages when large ESD currents flow, and these high voltages can still damage core transistors. Some ESD-protection structures use two diodes in series rather than one diode, but such stacked diodes are undesirable in some environments due to the increased voltage drop of two diodes in series.
Silicon-Controlled Rectifiers (SCR's) have also been used successfully. Both an SCR and a diode may be used. However, simply having a diode and an SCR in an ESD-protection structure may produce erratic results that depend on the relative locations of the SCR and diode and other structures such as guard rings.
FIG. 2 shows a safe design window for an ESD protection device. I-V curve 94 shows the current flowing through a prior-art ESD structure as a function of the ESD pulse voltage.
Initially, at the start of an ESD event, the device is off. I-V curve 94 shows that the voltage rises from zero as a diode or other device turns on and conducts current until trigger voltage VTRIG. Above this trigger voltage, other devices in the ESD structure turn on, such as a MOS transistor or an SCR, allowing a larger current to flow. Just after trigger voltage VTRIG, as the current increases, the diode or SCR shunts the most current, and an avalanche current or similar mechanism may decrease the voltage, causing the snap-back of I-V curve 94. The lowest voltage during snap back is holding voltage VHOLD.
The holding voltage VHOLD should be greater than the power-supply voltage VDD to ensure that latch-up does not occur. Also, the maximum voltage, such as trigger voltage VTRIG, should be less than the device breakdown voltage VBD to ensure that permanent damage does not occur. Thermal failure can occur when breakdown voltage VBD is exceeded for too long of a period of time. IC reliability is enhanced when the ESD protection structure operates within the safe design window, so that I-V curve 94 operates between VDD and VBD.
Actual device curves may vary and show secondary effects not shown in simplified I-V curve 94. As IC processing technology improves and shrinks, VBD decreases due to thinner gate oxides and smaller device sizes in general. Also, VDD may be reduced. Thus the safe design window may shift and shrink.
FIG. 3 shows a design window for a single-SCR ESD structure manufactured by an advanced process. The advanced IC process uses smaller devices with a reduced VBD, and VDD has also been reduced. An ESD structure that uses a single SCR has an I-V characteristic shown by I-V curve 94. The holding voltage VHOLD is less than VDD in this example. The ESD structure will be susceptible to latch up failure.
Sometimes a guard ring is added to suppress latch up. A pair of connected diffusions that act as guard rings to suppress minority carriers may be added to a lateral SCR to increase the holding voltage. Multi-Ring Active Analogic Protection (MAAP) is sometimes used. However, the trigger voltage may still be increased above the breakdown voltage VBD.
FIG. 4 shows a design window for a dual-SCR ESD structure manufactured by an advanced process. This ESD structure has two SCR's that are stacked in series. An ESD structure that uses a single SCR has an I-V characteristic shown by I-V curve 94, while the stacked dual-SCR structure has an I-V characteristic shown by I-V curve 96. The holding voltage VHOLD of the stacked SCR curve 96 is now more than VDD, reducing susceptibility to latch up failure. However, the trigger voltage VTRIG of the stacked SCR's is greater than the device breakdown voltage VBD. The ESD structure likely will have lower reliability and be more susceptible to thermal failure. Also the slope of curve 96 is less than the slope of curve 94, so the on resistance RON is increased, which can lower ESD structure efficiency and increase the ESD structure turn-on time.
It is desired to have an ESD protection structure that has an I-V curve 94 that fits within the design window, even for advanced IC processes with tight design windows. It is desired to raise the holding voltage VHOLD to be greater than VDD, without increasing the trigger voltage VTRIG above the breakdown voltage VBD.
It is desired to have a single SCR to avoid increasing the trigger voltage VTRIG above the breakdown voltage VBD. An electro-static-discharge (ESD) protection circuit with one SCR and a PMOS transistor is desired. An ESD protection device featuring parallel PMOS and SCR paths to allow for better optimization is desirable. Tightly integrating a PMOS transistor and an SCR is desired.